Question aout T1 regression test
Hi every body:
We met some problems during the T1 regerssion test
The question has been listed in the following:
1 In the OpenSPARCT1 verification code(verif\monitor.v), I found that it contains some code like "`ifdef GATE_SIM" in some places . But after this sentence, there is no any operation which has been defined:
`ifdef GATE_SIM
`else
`ifdef RTL_SPARC0
................
`endif
Does it mean that when we do gate level simulation of T1, there is nothing with monitor.v? If it is true, how can we believe that the gate level simulation result is reliable? What's the coverage of gate level simulation of T1?
Additionally, in the code of cmp_top.v(verif\cmp_top.v), it contains some code like "`ifdef GATE_SIM_SPARC".
what's the difference between GATE_SIM and GATE_SIM_SPARC?
2 The regression test envirement of GATE level simulation is the same as RTL level or not ? Shall we change something in testbench or add some arguments in the command (sims)?
2 When we do core1_mini regression test on LINUX computer, finally we found that there are 67 tests has passed. There is 1 performance. We guess the reason is that we run regression without SAS, it should be done on sun computer. Is it true?
what is the difference between regression result with SAS and without SAS? Is it possible to run regression with SAS on normal LINUX computer?
3 We did't succeed in running core1_full regression. There are 11 fail tests. The fail test name is following:
exu_ecc_mixed_ce
exu_ecc_mixed_ue
exu_ecc_rs1_ce
exu_ecc_rs2_ce
exu_ecc_rs3_ce
exu_ecc_stuck_at
exu_ecc_ue
exu_ecc_ue_priority
tlu_stb2b_trap_100
tlu_stb2b_trap_101
tlu_stb2b_trap_60
what is the reason?
4 Who has succeeded in running chip 8 regression? Must we do it on sun computer?
we will appreciate your help! Thanks a lot!
