RAM syntheisis
I almost completed synthesizing all the blocks exept SRAMS.
Memory compiler generatd RAM has following ports
output [127:0]QA;
inputCLKA;
inputCENA;
input [3:0] AA;
inputCLKB;
inputCENB;
input [3:0] AB;
input [127:0]DB;
input [2:0] EMAA
whereas OpensparcT1 rtl has the followig ports
input [127:0] din; // data input--> DB
input [15:0]rd_wl;// read addr
input [15:0]wr_wl; // write addr
input read_en;>CENA
input wr_en;//used in conjunction with->CENB
// word_wen and byte_wen
input rst_tri_en ; // gates off writes during SCAN.
input rclk;->CLKA,CLKB
input se, si ;
input reset_l;
input sehold; // hold scan in data.
output [127:0] dout;-->QA
output so;
Now, the problem is with the extra pins that RTL is having compared
to memory compiler o/p..
I tried to put a wrapper around the actual .But there is some glue logic
also to be implemented because ofrst_l,andsehold.Of course ,se,so
are not used.
And the address byte is 16 bit in the actual RTLcompared to 4-bit.
A 16 to 4 decoder is used.
I need somebody who can help me in this regard, Plz.
Most of my syntheisis work will be finished if I can close this issue.
If it is possible , I'm expecing a detailed reply .
best regards
nag
