Ideas
Welcome to the OpenSPARC general forums.We are just starting the community around OpenSPARC and would like to get your input on what you would like to see in support of this community. Our engineering team is working hard to get the bits available.
While we're waiting, there are several topics I think we could start sharing ideas about. For example:
1. Let's create a "Chipipedia" that helps define some of the terms we commonly use, but
2. If you could choose a perfect license for the code, what would it be?
3. What are some applications where multi-threading might shine?
4. (for you students) What is the hardest part to learn around chip design?
Any other thoughts?
Dwayne Lee
OpenSPARC community manager ATM
On a reply to number 2 I think it would be best if it would be an OSI approved license, let it be a custom license or an already existing one like
1. (L)GPL
2. BSD
etc, though I think GPL would be somewhat impossible since it will be used in propierty products as well.
So far this project sounds like a brilliant idea, I've always wanted to work with SPARC technology but the costs were always the bottleneck for me, I think this can make a change :)
Yorick Terweijden
First, let me take this opertunity to thank Sun for such a valuable, and generous, donation to the community.
Here are my thoughts:
1) It's my opinion that, in general terms, if someone is hoping to understand the complexities of many thousands of lines of verilog and the micro-architecture of a cutting edge CPU, then the terminology involved is really the least of their concerns. Opposed to having a website dedicated to such matters, it would be better if a site was dedicated to the micro-architectural details of the design, the design methodology, verification methodologies and tool-flow, etc... From my own personal experience, it precisely these things that are often only learnt through experience "in-the-field" and not in a text-book. I would really like to understand the design-flow: from the architecting of the CPU (behavioural model of the micro-architecture, finding performance bottle necks, etc...), refining the implementation from purely behavioural to synthesisable RTL/full custom (a)synchronous components, and the verification methodology used when carrying this out.
2) I don't really care about the license, since it's unlikely (pretty much impossible) for anyone to fabricate one of these devices for themselves. It should however ensure that IP issues, "you've seen my code, so now you cannot work on any thing else in this area for X years", etc.. are non-existent. I'm not sure to what extend it will be necessary to mandate that user modification be made public also; I'm not sure that hardware design lends itself as well to the incremental design flow found in open source software development as does software.
3) The usual: Web server, database etc...
4) The hardest part, for me, is the fact that to enhance your skills, you have to have access to very expensive, and complicated software that is completely out of the reach of the average person. I would like to design a couple of things in, say, Verilog, however, unless I have a license for a suitable HDL simulator I cannot. Whereas with software, one only has to download gcc and start typing away, with hardware, one either has to try and find the free equivalents: ng-spice, systemc, (public-domain EDA tools developed in universities) etc... ,find "fixed" copies of commercial tools, or try and get access to some academic licenses from your university.
One question I was wanting to ask: Are there any plans to open source the associated platform infrastructure on top of which the SPARC CPU will simulate. For example, will the model come with the necessary behavioural models to simulate the interconnect/memory subsystems? If not, will the model be limited to simulating under the test benches?
Thanks,
Stephen
Hi
One place where multi-threading is widely used is in
network processors. It seems to me that the T1 with
some appropriate hardware acceleration could be a
programmer friendly network processor.
Where can one find some detailed technical information
on the T? Is there any place where Amba AHB periperals
could be bolted on.
Kent
That is exactly what the CDDL was created for. CDDL is an OSI license, unlike the GPL it has provisions for propriatery products and unlike the GPL it is file based not project based so it also has many of the advantages of the BSD license as well.
For more info on the CDDL see here: http://opensolaris.org/os/about/faq/licensing_faq/
Note I am not an lawyer nor am I saying that OpenSPARC will be CDDL, I'm just pointing out that (L)GPL and BSD are not the only options and there is a solution to the issue you raised.
Sun is already using CDDL for OpenSolaris and many other projects as well.
I am a student.
My answer to #4 is couple of questions:
1) Are you open sourcing the HDL ? or also transistor level Schematic?
2) How about the softwares used to develope & test this components? Will they be freely available too? H-Spice?
3) I can visualize a software being developed by opensource community. You can compile and see if it works. Hardware? I remember developing a simple processor and simulating it. Simulation worked fine, but when we dumped it into a FPGA and tried, there were a lot of timing issues. I guess if you are kind enough to explain how this are done in real life, it would be cool.
Thats it for now.
Thanks.
Khaled
> I am a student.
>
> My answer to #4 is couple of questions:
> 1) Are you open sourcing the HDL ? or also
> transistor level Schematic?
We are only open sourcing the Verilog HDL.
> 2) How about the softwares used to develope &
> test this components? Will they be freely available
> too? H-Spice?
Test suite and verification environment will be provided to
verify the RTL.
H-SPICE is a commerical product which you need to license from Synopsys. It maybe available at your university or search the web for a opensource version.
>
> 3) I can visualize a software being developed by
> opensource community. You can compile and see if it
> works. Hardware? I remember developing a simple
> processor and simulating it. Simulation worked fine,
> but when we dumped it into a FPGA and tried, there
> were a lot of timing issues. I guess if you are kind
> enough to explain how this are done in real life, it
> would be cool.
>
Stay tuned as someone will explain it on the forum
> Thats it for now.
> Thanks.
> Khaled
>
> While we're waiting, there are several topics I think
> we could start sharing ideas about. For example:
>
> 1. Let's create a "Chipipedia" that helps define some
> of the terms we commonly use, but
[ Sournds like a good idea. As the community grows everyone talks the same language.
>
> 2. If you could choose a perfect license for the
> code, what would it be?
>
> 3. What are some applications where multi-threading
> might shine?
>
> 4. (for you students) What is the hardest part to
> learn around chip design?
>
> Any other thoughts?
>
> Dwayne Lee
> OpenSPARC community manager ATM
Now, let assume we want to use opensparc in a SOC embedded application, do we need to get a separate license from sparc international?
Can the number of cores in design be configured? (Minimum seems to be 4 cores)
This is an interesting development. Do you See sun becoming a strong contender in the SOC area against the leaders like ARM?
> Now, let assume we want to use opensparc in a SOC
> embedded application, do we need to get a separate
> license from sparc international?
Sun has only disclosed that they will license the technology under an Open Source license. We will have to wait for some clarification from Sun
>
> Can the number of cores in design be configured?
> (Minimum seems to be 4 cores)
It is my understanding that the design can be programmed to use 1 through 8 cores.
>
> This is an interesting development. Do you See sun
> becoming a strong contender in the SOC area against
> the leaders like ARM?
From the press release and F AQ it seems that Sun is
more interested in expanding its SPARC community.
I thought one of SUN's main goal is to make Sparc platform more popular.
Going from verilog HDL to transistor level design sounds like a big step to me. I am sure a lot of optimization will be required at transistor level.
How does SUN expect companies to actually invest a great deal of money and effort to clone the T1 processor?
I was wondering if the verilog HDL code can be transferred to a FPGA and tried out? I highly doubt in the existence of such a FPGA.
I am just really curious about what might this OpenSparc lead to and what can i possibly do.
There are many ways this can work:
- various parties start providing physical implementations for assorted fabs that can be licensed from them
- some may provide this for the whole chip, but more likely they will do it for just the core or some variant of that.
- regarding FPGAs, these days they are getting bigger and bigger and it will be really interesting to see what can fit. FPGAs can make hardware open source look more like s/w open source so that people can check out source, compile it into an FPGA, make some changes, verify and check it back in, and you save the time and cost involved with building silicon.
So looks like there are many possibilities for doing prototyping with FPGAs etc. and then casting into silicon when verifiied (perhaps with a h/w accelerator).
When the HDL is released, there should also be some synthesis scripts.
Current generation FPGA's have a capacity of about 200 Logic units. In future, the FPGA capacity will also increase.
As a student on the 4th question, I agree with Stephenry on the point that it's the lack of developpement tools that is the main issue.
I hope the opensparc initiative will quickly create free tools and help to create a wide free hardware community
As far as I am concerned, I don't think I'll be able to work on a project such as open Sparc, but I'm very enthousiastic about creating free hardware design, not only for computer world, and I hope that opensparc will help all people with the same willing
We hope that there are tools that do become available to the community. Here is one example of an open source verilog simulator. http://eetimes.com/news/design/showArticle.jhtml?articleID=174402073
Hi Kent,
I'm having Bill look into the best place to bolt on for AMBA peripherals. - will let you know
A variety of information will be available around the T1 and diags. when this is actually released. There is some information in papers which have been published (ie Hot Chips - summer 04, IEEE Micro paper - spring 05, Spring Processor Forum - 05, ISSCC paper and presentation - upcoming, and several white papers)
Looks like there are several new open source tools that arepopping up. In the latest issue of EE Times, there is thisarticle... http://www.eetimes.com/news/design/technology/showArticle.jhtml?articleID=17710 1584
And you can interface to several different tools usingElectric, http://www.staticfreesoft.com -- richard
Well the simple examples I have given so far were just for illustration purposes.
This processes is more or less and "organic". If is build of small FUs. The instructions are implied therefore no decoding is involved. (I.e., the instruction appear in recurring patters therefore they are deducible by the position they occupy in the instruction stream.) In the simplest case the whole processor is implemented using only a move instruction. The FUs perform simple operations. The system has registers which are hardwired to the FUs. On writing to a hardwired register which purse as an input to a FU would result in the resultant value will be placed in a hardwired register.
Computation is achieved side effects of moving the registers. (When input registers are written the output registers will have a value of the operation.) A number of these moves happen in parallel. The compiler should packet number of these moves (perhaps in order or out of order) so that all the many of the independent instructions are executed in parallel. The parallelism is only limited by the number of parallel moves and the availability of FUs. (To gain maximum leverage there should be as many FUs, for a given operations, equivalent to the number of parallel operation generally found in programmes and the parallel moves that are possible should be as much as the number of parallel instructions generally possible in programmes.)
FUs can also be also added and removed to extend or change the capabilities.
2006 Suminda Sirinath Salpitikorala Dharmasena. All rights reserved.
This does not constitute public disclosure. This is previledged infomation. Please keep this information as private to the forum and its users.
I am interested about the design flow of opensparc t1 development. Can you experts of sun post it with the eda tools name ?thank you
The EDA tools needed for OpenSPARC T1 are listed
on opensparc.net website, see "EDA tools requirements"
under
http://opensparc-t1.sunsource.net/download_hw.html
Also, FAQ page :
http://opensparc.sunsource.net/nonav/faq.html#q_33
and more details are in the
OpenSPARC T1 Design and Verification document
in the tar file.
Thank you for your reply. I think i have not expressed it clearly. I mean when opensparc T1 core would be designed, how to assure its performance to arrive your specification. And how to schedule the architecture of T1 ? Thanks
1. There are many performance measurement tests written to compare the
performance of the design Vs Expected performance. These tests are included
in the Chip design and Verification package.
2. At software level, using Architecture model and performance tracing/measurement
tools, you can measure the performance and see if it meets the expectations or not.
You need to use Architecture and Performance modeling package for this.
yeah, i think so. this the what i want to know. which tool? can you give me some hints. thank you very much.
Here are the specific tools for two different packages :
1. The tests in Chip design & Verification package are for running using Verilog
simulator. You can use VCS or NCVerilog simulator for these tests.
2. Architecture and Performance modeling package includes SAM simulator using
SAS (SPARC Architecture Simulator).
I'm a graduate who has just started learning verilog HDL.Can I know what is a synthesizable Verilog HDL code?Is it that "only behavioral level of abstraction not synthesizable"?
kindly someone please answer my question!!!
> I'm a graduate who has just started learning verilog HDL.
>
> Can I know what is a synthesizable Verilog HDL code?
As I understand it, synthesizable Verilog is Verilog code written to a set of coding standards that allow it to be run through a softtware tool chain that can generate an actual, functioning chip design.(It is definitely not just a behavioral model)
OpenSPARC T1's Verilog code is fully synthesizable -- in fact, projects are already synthesizing hardware designs out of it, including FPGA designs.
kindly someone please prescribe any free online tutorials on "writing testbenches".
is there any specific way to write an rtl code professioanlly...are there any specific things to be followed.
IEC/IEEE 62142-2005 is the current standard defining the RTL subset of the Verilog language.Alan FeldsteinCosmic Horizon http://www.alanfeldstein.com/
hi, many verilog textbook introduce how to write testbenched, you can goto bookstore to buy one, and follow it
